2014-05-12 10:46:53 +02:00
|
|
|
/*@!Encoding:1252*/
|
|
|
|
|
|
|
|
includes
|
|
|
|
{
|
2014-05-27 13:03:56 +02:00
|
|
|
#include "include\ModbusUdpClientCommon.cin"
|
2014-06-17 16:21:45 +02:00
|
|
|
#include "include\DeviceInformation.cin"
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
variables
|
|
|
|
{
|
2014-05-21 13:26:45 +02:00
|
|
|
msTimer gtRead;
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
on preStart
|
|
|
|
{
|
|
|
|
writeClear(0);
|
2014-05-21 13:38:59 +02:00
|
|
|
setStartdelay(10);
|
2014-06-17 16:28:29 +02:00
|
|
|
OutputDebugLevel = Warning;
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
on start
|
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
DeviceInit(@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::Vendor);
|
2014-05-21 13:26:45 +02:00
|
|
|
ModbusInit();
|
|
|
|
|
2014-06-17 16:21:45 +02:00
|
|
|
ModbusReadOutBits(gDevOutputBitAddr, @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::OutputBits);
|
|
|
|
ModbusReadOutRegisters(gDevOutputRegAddr, @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::OutputRegisters);
|
2014-05-26 12:07:04 +02:00
|
|
|
|
2014-06-17 18:41:05 +02:00
|
|
|
if (@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Config::Interval > 0)
|
|
|
|
setTimerCyclic(gtRead, 1, @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Config::Interval);
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Modbus events ----------------------------------------------------------------------
|
|
|
|
void OnModbusReadBitsFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
2014-05-26 12:07:04 +02:00
|
|
|
word i;
|
2014-05-21 13:29:29 +02:00
|
|
|
|
|
|
|
switch (error)
|
|
|
|
{
|
|
|
|
case Exception:
|
|
|
|
break;
|
|
|
|
case Timeout:
|
|
|
|
break;
|
|
|
|
case FinalTimeout:
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputBits");
|
2014-05-21 13:29:29 +02:00
|
|
|
for (i = 0; i < @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::InputBits; i++)
|
2014-05-26 12:07:04 +02:00
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::InputBits[i] = -1;
|
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputBits");
|
2014-05-21 13:29:29 +02:00
|
|
|
break;
|
|
|
|
}
|
2014-05-15 14:43:52 +02:00
|
|
|
}
|
2014-05-21 13:29:29 +02:00
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
void OnModbusReadRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
2014-05-15 14:43:52 +02:00
|
|
|
{
|
2014-05-26 12:07:04 +02:00
|
|
|
byte i;
|
2014-05-21 13:29:29 +02:00
|
|
|
|
|
|
|
switch (error)
|
|
|
|
{
|
|
|
|
case Exception:
|
|
|
|
break;
|
|
|
|
case Timeout:
|
|
|
|
break;
|
|
|
|
case FinalTimeout:
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputRegisters");
|
2014-05-21 13:29:29 +02:00
|
|
|
for (i = 0; i < @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::InputRegisters; i++)
|
2014-05-26 12:07:04 +02:00
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::InputRegisters[i] = -1;
|
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputRegisters");
|
2014-05-21 13:29:29 +02:00
|
|
|
break;
|
|
|
|
}
|
2014-05-15 14:43:52 +02:00
|
|
|
}
|
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
void OnModbusWriteBitFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusWriteRegisterFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusWriteMasksFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusReadWriteRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusWriteBitsFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusWriteRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2014-05-12 10:46:53 +02:00
|
|
|
|
2014-05-27 13:03:56 +02:00
|
|
|
void OnModbusReadBitsSuccess(struct ModbusResReceiveBits mbres, byte bitStatus[], struct ModbusReqRead mbreq)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
word i, offset;
|
2014-05-21 13:29:29 +02:00
|
|
|
|
2014-06-17 16:21:45 +02:00
|
|
|
switch (mbres.Header.FuncCode) // We assume that we separate between 0x01 and 0x02 even though the address space may be the same
|
2014-05-21 13:29:29 +02:00
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
case 0x01: // Read output bits
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "OutputBits");
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
offset = mbreq.Address - gDevOutputBitAddr; // Get the offset to the base output bit address
|
|
|
|
for (i = 0; i < mbreq.Count; i++)
|
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputBits[i + offset] = bitStatus[i];
|
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "OutputBits");
|
|
|
|
break;
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
|
|
|
|
case 0x02: // Read input bits
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputBits");
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
offset = mbreq.Address - gDevInputBitAddr; // Get the offset to the base input bit address
|
|
|
|
for (i = 0; i < mbreq.Count; i++)
|
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::InputBits[i + offset] = bitStatus[i];
|
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputBits");
|
2014-05-21 13:29:29 +02:00
|
|
|
break;
|
|
|
|
}
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
2014-05-21 13:29:29 +02:00
|
|
|
|
2014-05-27 13:03:56 +02:00
|
|
|
void OnModbusReadRegistersSuccess(struct ModbusResReceiveRegisters mbres, struct ModbusReqRead mbreq)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
word i, offset;
|
2014-05-15 14:43:52 +02:00
|
|
|
|
2014-06-17 16:21:45 +02:00
|
|
|
switch (mbres.Header.FuncCode) // We assume that we separate between 0x03 and 0x04 even though the address space may be the same
|
2014-05-15 14:43:52 +02:00
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
case 0x03: // Read output registers
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "OutputRegisters");
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
offset = mbreq.Address - gDevOutputRegAddr; // Get the offset to the base output register address
|
|
|
|
for (i = 0; i < mbreq.Count; i++)
|
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputRegisters[i + offset] = mbres.Data[i];
|
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "OutputRegisters");
|
2014-05-15 14:43:52 +02:00
|
|
|
break;
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
|
|
|
|
case 0x04: // Read input registers
|
2014-05-26 12:07:04 +02:00
|
|
|
sysBeginVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputRegisters");
|
2014-06-17 16:21:45 +02:00
|
|
|
|
|
|
|
offset = mbreq.Address - gDevInputRegAddr; // Get the offset to the base input bit address
|
|
|
|
for (i = 0; i < mbreq.Count; i++)
|
|
|
|
@sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::InputRegisters[i + offset] = mbres.Data[i];
|
|
|
|
|
2014-05-26 12:07:04 +02:00
|
|
|
sysEndVariableStructUpdate("%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data", "InputRegisters");
|
2014-05-21 13:29:29 +02:00
|
|
|
break;
|
2014-05-15 14:43:52 +02:00
|
|
|
}
|
2014-05-12 10:46:53 +02:00
|
|
|
}
|
2014-05-21 13:29:29 +02:00
|
|
|
|
2014-05-15 14:43:52 +02:00
|
|
|
void OnModbusWriteBitSuccess(struct ModbusResConfirmSingle mbc)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
|
|
|
}
|
2014-05-15 14:43:52 +02:00
|
|
|
void OnModbusWriteRegisterSuccess(struct ModbusResConfirmSingle mbc)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
|
|
|
}
|
2014-05-15 14:43:52 +02:00
|
|
|
void OnModbusWriteBitsSuccess(struct ModbusResConfirmMultiple mbc)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
|
|
|
}
|
2014-05-15 14:43:52 +02:00
|
|
|
void OnModbusWriteRegistersSuccess(struct ModbusResConfirmMultiple mbc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
void OnModbusWriteMasksSuccess(struct ModbusResConfirmMasks mbc)
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2014-05-27 13:03:56 +02:00
|
|
|
void OnModbusClientPanics(enum FatalErrors reason)
|
|
|
|
{
|
|
|
|
writeLineEx(0, 4, "<%NODE_NAME%> FATAL! %d", reason);
|
|
|
|
switch(reason)
|
|
|
|
{
|
|
|
|
case ParsingBuffer:
|
|
|
|
case ModbusPackageWasSplit:
|
|
|
|
case DeviceCodeUnknown:
|
|
|
|
case VendorIdUnknown:
|
|
|
|
runError(1001, reason);
|
|
|
|
break;
|
|
|
|
case ConnectionError:
|
|
|
|
gtRead.Cancel();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2014-05-12 10:46:53 +02:00
|
|
|
|
|
|
|
// Key events -------------------------------------------------------------------------
|
2014-05-21 13:26:45 +02:00
|
|
|
on timer gtRead
|
|
|
|
{
|
2014-06-17 16:21:45 +02:00
|
|
|
ModbusReadRegisters(0x0000, @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::InputRegisters);
|
|
|
|
ModbusReadBits(0x0000, @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::InputBits);
|
2014-06-17 16:28:29 +02:00
|
|
|
//this.Cancel();
|
2014-05-21 13:26:45 +02:00
|
|
|
}
|
|
|
|
|
2014-05-21 13:29:29 +02:00
|
|
|
on sysvar %BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputBits
|
2014-05-15 14:43:52 +02:00
|
|
|
{
|
2014-06-16 09:23:21 +02:00
|
|
|
word count, i;
|
2014-05-21 13:29:29 +02:00
|
|
|
byte bitStatus[1968];
|
2014-05-26 12:07:04 +02:00
|
|
|
|
|
|
|
count = @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::OutputBits;
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
bitStatus[i] = @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputBits[i];
|
|
|
|
|
2014-06-16 09:23:21 +02:00
|
|
|
ModbusWriteBitsB(0, count, bitStatus);
|
2014-05-15 14:43:52 +02:00
|
|
|
}
|
2014-05-21 13:29:29 +02:00
|
|
|
on sysvar %BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputRegisters
|
2014-05-12 10:46:53 +02:00
|
|
|
{
|
2014-05-26 12:07:04 +02:00
|
|
|
word count, i;
|
|
|
|
word regValues[123];
|
|
|
|
|
|
|
|
count = @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Info::OutputRegisters;
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
regValues[i] = @sysvar::%BUS_TYPE%%CHANNEL%::%NODE_NAME%::Data::OutputRegisters[i];
|
|
|
|
|
|
|
|
ModbusWriteRegisters(0x000, count, regValues);
|
|
|
|
}
|
|
|
|
|
|
|
|
on sysvar %BUS_TYPE%%CHANNEL%::%NODE_NAME%::Config::Interval
|
|
|
|
{
|
|
|
|
if (@this <= 0)
|
|
|
|
gtRead.Cancel();
|
|
|
|
else
|
|
|
|
setTimerCyclic(gtRead, @this);
|
2014-05-21 13:26:45 +02:00
|
|
|
}
|