796 lines
28 KiB
Plaintext
796 lines
28 KiB
Plaintext
/*@!Encoding:1252*/
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// The state machine in this file will use all functions of the Modbus Client and check the results
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// Use the SysVars to configure the test.
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// The states are:
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//
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// 0: Get device information [ -> OnModbusReadRegistersSuccess ]
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// 5: Reading output bits (check functionality of 0x01) [ -> OnModbusReadBitsSuccess ]
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// 10: Reading output registers (check functionality of 0x03) [ -> OnModbusReadRegistersSuccess ]
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// 20: Reading input bits (check functionality of 0x02) [ -> OnModbusReadBitsSuccess ]
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// 30: Reading input registers (check functionality of 0x04) [ -> OnModbusReadRegistersSuccess -> timr (30 or 130) ]
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// 40: Write Bits 0x0 - 0x9 to 1 (check functionality of 0x0F) [ -> OnModbusWriteBitsSuccess ]
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// 50: Write Bit 0x2 to 0 (check functionality of 0x05) [ -> OnModbusWriteBitSuccess -> timr ]
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// 60: Read Bits 0x0 - 0x9 and check whether result is (check result of 0x0F and 0x05: 1 1 0 1 1 1 1 1 1) [ -> OnModbusReadBitsSuccess ]
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// 70: Write 1 output registers 0x0 to 0x55555 (check functionality of 0x10) [ -> OnModbusWriteRegistersSuccess -> timr ]
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// 75: Read output register 0x0 and check (check result of 0x10) [ -> OnModbusReadRegistersSuccess ]
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// 80: Write output register 0x0 to 0x9999 (check functionality of 0x06) [ -> OnModbusWriteRegisterSuccess -> timr ]
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// 90: Read output register 0x0 (check result of 0x06) [ -> OnModbusReadRegistersSuccess ]
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// 100: Writing masks (&00F9 |0x006) to 0x0 (check functionality of 0x16) [ -> OnModbusWriteMasksSuccess -> timr ]
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// 110: Read output register 0x0 and check the success of 100 (check result of 0x16) [ -> OnModbusReadRegistersSuccess ]
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// 120: Read 3000 input bits (check whether read bit telegrams can be divided) [ -> OnModbusReadBitsSuccess ]
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// 130: [ -> OnModbusReadBitsSuccess -> timr ]
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// 140: Read 300 input registers (check whether read register telegrams can be divided) [ -> OnModbusReadRegistersSuccess ]
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// 145: [ -> OnModbusReadRegistersSuccess ]
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// 150: [ -> OnModbusReadRegistersSuccess -> timr (160 or 200) ]
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// 160: Write 3000 Bits at 0x0 to 0 [ -> OnModbusWriteBitsSuccess ]
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// 170: Write 3000 Bits at 0x0 to 0 [ -> OnModbusWriteBitsSuccess ]
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// 180: Write 200 registers (check whether telegrams can be divided) [ -> OnModbusWriteRegistersSuccess ]
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// 190: [ -> OnModbusWriteRegistersSuccess -> timr ]
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// 900: Testing the receive window size [ -> OnModbusReadBitsSuccess -> 900 ]
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// 900: Stop [ -> OnModbusReadBitsFailed ]
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// Function codes (tested functionality, check results, checked whether telegrams can be divided)
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// func result divided req (B+R)
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// 0x01 00 X (120) // Read Bits out
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// 0x02 20 X 120 // Read Bits in
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// 0x03 10 X (140) // Read Registers out
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// 0x04 30 X 140 // Read Registers in
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// 0x05 50 60 X // Write 1 Bit
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// 0x06 80 90 X // Write 1 Register
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// 0x0F 40 60 (160) // Write multiple Bits
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// 0x0F* 160 |___| 160 // Write multiple Bits with encoding
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// 0x10 70 75 180 // Write multiple Registers
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// 0x16 100 110 X // Mask Register
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// 0x17 |___| |___| |___| // Read/Write Registers
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// Don't forget to set up the device in SysVars
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includes
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{
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#include "include/DeviceInformation.cin"
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#include "include/ModbusUdp.cin"
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#include "include/ModbusClient.cin"
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}
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variables
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{
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word state = 0; // The current state of this machine
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byte s0i = 0; // some i for state 0
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struct device s0dev; // device struct for state 0
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byte s90i = 1; // some i for state 90
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msTimer timr; // a timer to give the device some time to refresh
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byte skipOutput = 0; // whether output checks shall be skipped (and output modules are present)
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}
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on preStart
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{
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setStartdelay(100);
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OutputDebugLevel = Debug;
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}
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on start
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{
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char ip[16];
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sysGetVariableString("Device::Config", "IP", ip, 16);
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DeviceInit(@sysvar::Device::Config::Vendor);
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ModbusInit(ip, @sysvar::Config::Modbus::Port, @sysvar::Config::Modbus::RequestTimeout, 1 /*retry*/);
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if (gSocketState < CONNECTING) // We are not connecting and not connected
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return;
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// Start the Test
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s0dev.Vendor = (enum Vendor)@sysvar::Device::Config::Vendor;
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s0i = _DeviceGetInformation((enum Vendor)@sysvar::Device::Config::Vendor); // get info from the device
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}
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on preStop
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{
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ModbusEnd();
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}
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void OnModbusReadBitsFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
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{
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char reason[100];
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struct ModbusReqRead mbreq;
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switch (error)
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{
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case Timeout:
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break;
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case FinalTimeout:
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strncpy(reason, "Timeout", elCount(reason));
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break;
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case Exception:
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snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
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break;
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case NotSent:
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strncpy(reason, "Impossible to send", elCount(reason));
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break;
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default:
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writeDbg(MbError, "OnModbusReadBitsFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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switch (state)
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{
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case 0:
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writeDbg(MbError, "State %d. Reading %d output bit from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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case 20:
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writeDbg(MbError, "State %d. Reading %d input bit from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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case 60:
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case 120:
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case 130:
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writeDbg(MbError, "State %d. Reading %d output bits from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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case 900:
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if (error == FinalTimeout)
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{
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writeDbg(MbInfo, "State %d. Packet timed out! Receive window size: %d", state, s90i-1);
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state = 910;
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stop();
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return;
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}
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else
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writeDbg(MbError, "State %d. Error while writing bit: %s", state, reason);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusReadBitsFailed()!", state);
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break;
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}
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runError(1001, 0);
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}
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void OnModbusReadBitsSuccess(struct ModbusResReceiveBits mbres, byte bitStatus[], struct ModbusReqRead mbreq)
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{
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byte i;
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word s6[1] = {0x5555};
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switch (state)
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{
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case 5:
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writeDbg(MbDebug, "State %d. Successfully read %d output bit from 0x%04X", state, mbreq.Count, mbreq.Address);
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ModbusReadOutRegisters(thisDev.Addr.Read.OutputRegisters, 1);
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state = 10;
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break;
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case 20:
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writeDbg(MbDebug, "State %d. Successfully read %d input bit from 0x%04X", state, mbreq.Count, mbreq.Address);
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ModbusReadInRegisters(thisDev.Addr.Read.InputRegisters, 1);
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state = 30;
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break;
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case 60:
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writeDbg(MbDebug, "State %d. Successfully read %d output bits from 0x%04X", state, mbreq.Count, mbreq.Address);
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for (i = 0; i < mbreq.Count; i++)
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{
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writeDbg(MbWarning, "i: %d, Status: %d, Expected: %d", i, bitStatus[i], (i != 2));
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if (bitStatus[i] != (i != 2))
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{
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writeDbg(MbError, "State of output bit %d was incorrect: %d (expected %d)", i, bitStatus[i], (i != 2));
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runError(1001, 0);
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return;
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}
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}
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// OK.
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writeDbg(MbDebug, "State %d. Status of these output bits was correct.", state);
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ModbusWriteRegisters(thisDev.Addr.Write.OutputRegisters, 1, s6);
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state = 70;
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break;
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case 120:
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state = 130;
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break;
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case 130:
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writeDbg(MbDebug, "State %d. Successfully received the Read-Bits telegrams (as expected)", state);
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timr.Set(1);
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break;
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case 900:
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if (gQueueSent.Size() > 0 || gQueuePending.Size() > 0)
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break;
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++s90i;
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for (i = 0; i < s90i && i < 100; i++)
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ModbusReadBits(thisDev.Addr.Read.InputBits, 1);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusReadBitsSuccess()!", state);
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runError(1001, 0);
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break;
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}
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}
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void OnModbusReadRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
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{
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char reason[100];
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struct ModbusReqRead mbreq;
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switch (error)
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{
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case Timeout:
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break;
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case FinalTimeout:
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strncpy(reason, "Timeout", elCount(reason));
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break;
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case Exception:
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snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
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break;
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case NotSent:
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strncpy(reason, "Impossible to send", elCount(reason));
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break;
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default:
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writeDbg(MbError, "OnModbusReadRegistersFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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switch (state)
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{
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case 0:
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case 10:
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case 110:
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case 75:
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writeDbg(MbError, "State %d. Reading %d output register from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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case 30:
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writeDbg(MbError, "State %d. Reading %d input register from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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case 90:
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case 140:
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case 145:
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case 150:
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writeDbg(MbError, "State %d. Reading %d output registers from 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusReadRegistersFailed()!", state);
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break;
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}
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runError(1001, 0);
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}
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void OnModbusReadRegistersSuccess(struct ModbusResReceiveRegisters mbres, struct ModbusReqRead mbreq)
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{
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switch (state)
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{
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case 0:
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s0i--;
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_DeviceParseRegister(s0dev, mbreq.Address, mbres.Data, 0);
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if (s0i == 0) // all requests completed
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{
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if (s0dev.DeviceIOs.OutputBits / 8 + s0dev.DeviceIOs.OutputRegisters < 2)
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{
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writeDbg(MbError, "Please connect more output! %d bits and %d registers are not enough, we need at least 1 word (2 bytes). (Input: %d bits, %d regs)", s0dev.DeviceIOs.OutputBits, s0dev.DeviceIOs.OutputRegisters, s0dev.DeviceIOs.InputBits, s0dev.DeviceIOs.InputRegisters);
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skipOutput = 1;
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//runError(1001, 0);
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//return;
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}
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state = 5;
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ModbusReadOutBits(thisDev.Addr.Read.OutputBits, 1);
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}
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break;
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case 10:
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writeDbg(MbDebug, "State %d. Successfully read %d output register from 0x%04X", state, mbreq.Count, mbreq.Address);
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ModbusReadInBits(thisDev.Addr.Read.InputBits, 1);
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state = 20;
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break;
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case 30:
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writeDbg(MbDebug, "State %d. Successfully read %d input register from 0x%04X", state, mbreq.Count, mbreq.Address);
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if (skipOutput)
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state = 130;
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timr.Set(1);
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break;
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case 75:
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writeDbg(MbDebug, "State %d. Successfully read %d input register from 0x%04X", state, mbreq.Count, mbreq.Address);
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if (mbres.Data[0] != 0x5555)
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{
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writeDbg(MbError, "State %d. Value of output register 0 was incorrect: 0x%04X (expected 0x5555). ModbusWriteRegisters failed!", state, mbres.Data[0]);
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runError(1001, 0);
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return;
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}
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ModbusWriteRegister(thisDev.Addr.Write.OutputRegisters, 0x9999);
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state = 80;
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break;
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case 90:
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writeDbg(MbDebug, "State %d. Successfully read %d output register from 0x%04X", state, mbreq.Count, mbreq.Address);
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if (mbres.Data[0] != 0x9999)
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{
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writeDbg(MbError, "State %d. Value of output register 0 was incorrect: 0x%04X (expected 0x9999). ModbusWriteRegister failed!", state, mbres.Data[0]);
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runError(1001, 0);
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return;
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}
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ModbusWriteMasks(thisDev.Addr.Write.OutputRegisters, 0x00F9, 0x0006);
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state = 100;
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break;
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case 110:
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writeDbg(MbDebug, "State %d. Successfully read %d output register from 0x%04X", state, mbreq.Count, mbreq.Address);
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if (mbres.Data[0] != 0x009F)
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{
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writeDbg(MbError, "State %d. Value of register at 0x%04X is incorrect: 0x%04X (expected 0x009F). ModbusWriteMasks failed!", state, mbreq.Address, mbres.Data[0]);
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runError(1001, 0);
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return;
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}
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writeDbg(MbDebug, "State %d. Successfully applied the masks at 0x%04X", state, mbreq.Address);
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ModbusReadInBits(thisDev.Addr.Read.InputBits, 3000);
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state = 120;
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if (s0dev.Vendor == Wago) // This test does not work with Wago
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state = 130;
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break;
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case 140:
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state = 145;
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break;
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case 145:
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state = 150;
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break;
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case 150:
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writeDbg(MbDebug, "State %d. Successfully received three Read-Registers telegrams (as expected)", state);
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if (skipOutput)
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state = 190;
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else
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{
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state = 160;
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if (s0dev.Vendor == Wago) // This test does not work with Wago
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state = 170;
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}
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timr.Set(1);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusReadRegistersSuccess()!", state);
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runError(1001, 0);
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break;
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}
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}
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void OnModbusWriteBitFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
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{
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char reason[100];
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struct ModbusReqWriteSingle mbreq;
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switch (error)
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{
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case Timeout:
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break;
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case FinalTimeout:
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strncpy(reason, "Timeout", elCount(reason));
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break;
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case Exception:
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snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
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break;
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case NotSent:
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strncpy(reason, "Impossible to send", elCount(reason));
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break;
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default:
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writeDbg(MbError, "OnModbusWriteBitFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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switch (state)
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{
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case 50:
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writeDbg(MbError, "State %d. Setting bit at 0x%04X did not work! Reason: %s", state, mbreq.Address, reason);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteBitFailed()!", state);
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break;
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}
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runError(1001, 0);
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}
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void OnModbusWriteBitSuccess(struct ModbusResConfirmSingle mbres)
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{
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byte i;
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switch (state)
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{
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case 50:
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writeDbg(MbDebug, "State %d. Successfully set bit at 0x%04X", state, mbres.Address);
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timr.Set(1);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteBitSuccess()!", state);
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runError(1001, 0);
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break;
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}
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}
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void OnModbusWriteRegisterFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
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{
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char reason[100];
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struct ModbusReqWriteSingle mbreq;
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switch (error)
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{
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case Timeout:
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break;
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case FinalTimeout:
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strncpy(reason, "Timeout", elCount(reason));
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break;
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case Exception:
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snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
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break;
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case NotSent:
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strncpy(reason, "Impossible to send", elCount(reason));
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break;
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default:
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writeDbg(MbError, "OnModbusWriteRegisterFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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switch (state)
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{
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case 80:
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writeDbg(MbError, "State %d. Writing output register at 0x%04X did not work! Reason: %s", state, mbreq.Address, reason);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteRegisterFailed()!", state);
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break;
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}
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runError(1001, 0);
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}
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void OnModbusWriteRegisterSuccess(struct ModbusResConfirmSingle mbres)
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{
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switch (state)
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{
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case 80:
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writeDbg(MbDebug, "State %d. Successfully set output register at 0x%04X to 0x%04X", state, mbres.Address, mbres.Value);
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timr.Set(1);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteRegisterSuccess()!", state);
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runError(1001, 0);
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break;
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}
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}
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void OnModbusWriteMasksFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
{
|
|
char reason[100];
|
|
struct ModbusReqWriteMasks mbreq;
|
|
|
|
switch (error)
|
|
{
|
|
case Timeout:
|
|
break;
|
|
case FinalTimeout:
|
|
strncpy(reason, "Timeout", elCount(reason));
|
|
break;
|
|
case Exception:
|
|
snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
|
|
break;
|
|
case NotSent:
|
|
strncpy(reason, "Impossible to send", elCount(reason));
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|
break;
|
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default:
|
|
writeDbg(MbError, "OnModbusWriteMasksFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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|
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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switch (state)
|
|
{
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case 100:
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writeDbg(MbError, "State %d. Applying masks &0x%04X |0x%04X at 0x%04X did not work! Reason: %s", state, mbreq.And, mbreq.Or, mbreq.Address);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteMasksFailed()!", state);
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break;
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}
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runError(1001, 0);
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}
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void OnModbusWriteMasksSuccess(struct ModbusResConfirmMasks mbres)
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{
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switch (state)
|
|
{
|
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case 100:
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writeDbg(MbDebug, "State %d. Successfully applied masks &0x%04X |0x%04X at 0x%04X", state, mbres.And, mbres.Or, mbres.Address);
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timr.Set(1);
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break;
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default:
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writeDbg(MbError, "I did not expect state %d in OnModbusWriteMasksSuccess()!", state);
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runError(1001, 0);
|
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break;
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}
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}
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|
|
|
|
|
|
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|
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|
|
|
|
|
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void OnModbusReadWriteRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
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{
|
|
char reason[100];
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struct ModbusReqReadWriteRegisters mbreq;
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|
|
|
switch (error)
|
|
{
|
|
case Timeout:
|
|
break;
|
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case FinalTimeout:
|
|
strncpy(reason, "Timeout", elCount(reason));
|
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break;
|
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case Exception:
|
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snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
|
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break;
|
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case NotSent:
|
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strncpy(reason, "Impossible to send", elCount(reason));
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break;
|
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default:
|
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writeDbg(MbError, "OnModbusReadWriteRegistersFailed: Unkown error: %d", error);
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OnModbusClientPanics(SwitchArgumentInvalid);
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return;
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}
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|
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memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
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|
|
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switch (state)
|
|
{
|
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default:
|
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writeDbg(MbError, "I did not expect state %d in OnModbusReadWriteRegistersFailed()!", state);
|
|
break;
|
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}
|
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runError(1001, 0);
|
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}
|
|
|
|
|
|
|
|
|
|
|
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|
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void OnModbusWriteBitsFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
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{
|
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char reason[100];
|
|
struct ModbusReqWriteBits mbreq;
|
|
|
|
switch (error)
|
|
{
|
|
case Timeout:
|
|
break;
|
|
case FinalTimeout:
|
|
strncpy(reason, "Timeout", elCount(reason));
|
|
break;
|
|
case Exception:
|
|
snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
|
|
break;
|
|
case NotSent:
|
|
strncpy(reason, "Impossible to send", elCount(reason));
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "OnModbusWriteBitsFailed: Unkown error: %d", error);
|
|
OnModbusClientPanics(SwitchArgumentInvalid);
|
|
return;
|
|
}
|
|
|
|
memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
|
|
|
|
switch (state)
|
|
{
|
|
case 40:
|
|
case 160:
|
|
case 170:
|
|
writeDbg(MbError, "State %d. Writing %d bits at 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "I did not expect state %d in OnModbusWriteBitsFailed()!", state);
|
|
break;
|
|
}
|
|
runError(1001, 0);
|
|
}
|
|
void OnModbusWriteBitsSuccess(struct ModbusResConfirmMultiple mbres)
|
|
{
|
|
word s17[200];
|
|
|
|
switch (state)
|
|
{
|
|
case 40:
|
|
writeDbg(MbDebug, "State %d. Successfully set %d bits at 0x%04X", state, mbres.Count, mbres.Address);
|
|
ModbusWriteBit(thisDev.Addr.Write.OutputBits+2, 0);
|
|
state = 50;
|
|
break;
|
|
case 160:
|
|
state = 170;
|
|
break;
|
|
case 170:
|
|
writeDbg(MbDebug, "State %d. Successfully received two(?) Write-Bits telegrams (as expected)", state);
|
|
ModbusWriteRegisters(thisDev.Addr.Write.OutputRegisters, 200, s17);
|
|
state = 180;
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "I did not expect state %d in OnModbusWriteBitsSuccess()!", state);
|
|
runError(1001, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void OnModbusWriteRegistersFailed(enum ModbusRequestError error, enum ModbusException ex, struct ModbusApHeader mbap)
|
|
{
|
|
char reason[100];
|
|
struct ModbusReqWriteRegisters mbreq;
|
|
|
|
switch (error)
|
|
{
|
|
case Timeout:
|
|
break;
|
|
case FinalTimeout:
|
|
strncpy(reason, "Timeout", elCount(reason));
|
|
break;
|
|
case Exception:
|
|
snprintf(reason, elCount(reason), "Exception: %s", ModbusExceptions[ex-1]);
|
|
break;
|
|
case NotSent:
|
|
strncpy(reason, "Impossible to send", elCount(reason));
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "OnModbusWriteRegistersFailed: Unkown error: %d", error);
|
|
OnModbusClientPanics(SwitchArgumentInvalid);
|
|
return;
|
|
}
|
|
|
|
memcpy_n2h(mbreq, gQueueAck[mbap.TxID].Buffer);
|
|
|
|
switch (state)
|
|
{
|
|
case 70:
|
|
case 180:
|
|
case 190:
|
|
writeDbg(MbError, "State %d. Writing %d registers at 0x%04X did not work! Reason: %s", state, mbreq.Count, mbreq.Address, reason);
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "I did not expect state %d in OnModbusWriteRegistersFailed()!", state);
|
|
break;
|
|
}
|
|
runError(1001, 0);
|
|
}
|
|
void OnModbusWriteRegistersSuccess(struct ModbusResConfirmMultiple mbres)
|
|
{
|
|
switch (state)
|
|
{
|
|
case 70:
|
|
writeDbg(MbDebug, "State %d. Successfully set %d output registers at 0x%04X", state, mbres.Count, mbres.Address);
|
|
timr.Set(1);
|
|
break;
|
|
case 180:
|
|
state = 190;
|
|
break;
|
|
case 190:
|
|
writeDbg(MbDebug, "State %d. Successfully received two Write-Registers telegrams (as expected)", state);
|
|
timr.Set(1);
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "I did not expect state %d in OnModbusWriteRegistersSuccess()!", state);
|
|
runError(1001, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void OnModbusClientPanics(enum FatalErrors reason)
|
|
{
|
|
switch (reason)
|
|
{
|
|
case ParsingBuffer:
|
|
writeDbg(MbError, "State %d. FATAL ERROR while parsing received buffer", state);
|
|
break;
|
|
case ModbusPackageWasSplit:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: Modbus package was split", state);
|
|
break;
|
|
case DeviceCodeUnknown:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: Device code unknown", state);
|
|
break;
|
|
case VendorIdUnknown:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: Vendor Id unknown", state);
|
|
break;
|
|
case ConnectionError:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: Connection Error", state);
|
|
break;
|
|
case FuncCodeIncorrect:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: FuncCode Incorrect", state);
|
|
break;
|
|
case AddressFailure:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: Some Modbus Address Failure", state);
|
|
break;
|
|
case SwitchArgumentInvalid:
|
|
writeDbg(MbError, "State %d. FATAL ERROR: A argument of a switch statement is incorrect");
|
|
break;
|
|
}
|
|
|
|
stop();
|
|
runError(1001, 0);
|
|
}
|
|
|
|
|
|
on timer timr
|
|
{
|
|
byte s3[10] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
|
|
byte s15[3000];
|
|
|
|
switch(state)
|
|
{
|
|
case 30:
|
|
ModbusWriteBitsB(thisDev.Addr.Write.OutputBits, 10, s3);
|
|
state = 40;
|
|
break;
|
|
case 50:
|
|
ModbusReadOutBits(thisDev.Addr.Read.OutputBits, 10);
|
|
state = 60;
|
|
break;
|
|
case 70:
|
|
ModbusReadOutRegisters(thisDev.Addr.Read.OutputRegisters, 1);
|
|
state = 75;
|
|
break;
|
|
case 80:
|
|
ModbusReadOutRegisters(thisDev.Addr.Read.OutputRegisters, 1);
|
|
state = 90;
|
|
break;
|
|
case 100:
|
|
ModbusReadOutRegisters(thisDev.Addr.Read.OutputRegisters, 1);
|
|
state = 110;
|
|
break;
|
|
case 130:
|
|
ModbusReadRegisters(thisDev.Addr.Read.InputRegisters, 300);
|
|
state = 140;
|
|
break;
|
|
case 160:
|
|
ModbusWriteBitsB(thisDev.Addr.Write.OutputBits, 3000, s15);
|
|
break;
|
|
case 170:
|
|
ModbusWriteBitsB(thisDev.Addr.Write.OutputBits, 1000, s15);
|
|
break;
|
|
case 190:
|
|
ModbusReadBits(thisDev.Addr.Read.InputBits, 1);
|
|
thisDev.ReceiveWindow = 0xFF; // Set receive window to maximum to test the limit
|
|
state = 900;
|
|
break;
|
|
default:
|
|
writeDbg(MbError, "I did not expect state %d in timer timr!", state);
|
|
break;
|
|
}
|
|
} |